As far as the processor hardware is concerned, there are two basic types of concepts to implement the processor hardware architecture.
What is RISC architecture?
RISC is acronym for Reduced Instruction Set Computing. In this architecture a microprocessor is designed to perform a smaller number of types of instructions so that it can operate at a higher speed (perform more millions of instructions per second, or MIPS).
Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation. That is why less instruction means fast in operations. Pipelining is one of the unique feature of RISC. It is performed by overlapping the execution of several instructions in a pipeline fashion.
Example: Apple iPod and Nintendo DS etc.
What is CISC architecture?
CISC is acronym for Complex Instruction Set Computing. CISC architecture are designed to decrease the memory cost. The large programs need more storage, thus increasing the memory cost and large memory becomes more expensive.
To solve these problems, in CISC architecture the number of instructions per program is reduced by embedding the number of operations in each instruction. Thereby the instructions are more complex.
Example: IBM 370/168, VAX 11/780, Intel 80486 etc.
Difference between RISC and CISC architecture:
# | RISC | CISC |
---|---|---|
1 | Simple instructions taking one cycle. | Complex instructions taking multiple cycle. |
2 | Very few instructions refer memory. | Most of instructions may refer memory. |
3 | Instructions are executed by hardware. | Instructions are executed by micro-program. |
4 | Fixed format instructions. | Variable format instructions. |
5 | Few instructions. | Many instructions. |
6 | Complex addressing modes are synthesized in software. | Supports complex addressing modes. |
7 | Multiple register sets. | Single register set. |
8 | Highly pipelined. | Not pipelined or less pipelined. |
9 | Conditional jump can be based on a bit anywhere ¡n memory. | Conditional jump is usually based on status register bit. |
10 | Complexity is in the compiler | Complexity is in the micro-program |
11 | Few addressing mode and most instructions have register to register addressing mode | Many addressing modes |